Semiconductors that include integrated circuits (IC) operate at increasingly higher frequencies and data rates and at lower voltages. In turn, increasingly higher semiconductor operating frequencies (higher IC switching speeds) require that voltage response times to the IC must be faster. Lower operating voltages require that allowable voltage variations (ripple) and noise become smaller.
For example, a semiconductor, such as a microprocessor IC, switches and begins an operation, it calls for power to support the switching circuits. If the response time of the voltage supply is too slow, the microprocessor will experience a voltage drop or voltage droop that will exceed the allowable ripple voltage and reduce the circuit noise margin and the IC will malfunction. Additionally, as the IC powers up, a slow response time will result in voltage overshoot. Voltage droop and overshoot must be controlled within allowable limits by the use of capacitors that are close enough to the IC to provide or absorb power within the appropriate response time.
Ultimately, then, the reduction of noise in the power and ground (return) lines and the need to supply sufficient current to accommodate faster circuit switching become increasingly important. In order to provide low noise and stable power to the IC, low impedance in the power distribution system is required. In conventional printed wiring board (PWB) semiconductor packages, impedance is reduced by the use of surface mount capacitors.
A capacitor reduces impedance in the circuit across a relatively small frequency range around its resonant frequency. Therefore, many capacitors are chosen with different resonant frequencies to accomplish reduced impedance across a wide frequency range. The resonant frequency of a capacitor is dependent on its type, size, termination separation and the circuit resistance and inductance of its electrical interconnection to the semiconductor. The degree of impedance reduction at its resonant frequency is also proportional to the amount of capacitance so capacitors are typically interconnected in parallel to maximize total capacitance.
FIG. 1 is an electrical schematic for a typical placement of capacitors. Shown is a power supply, an IC and the capacitors 4, 6, 8, which represent high value, mid-range value and small value capacitors, respectively, used for impedance reduction and minimizing voltage droop and dampening voltage overshoot. In this electrical schematic, the total number of capacitors shown is 6 capacitors. In practice however, this total may reach several hundred.
Conventional designs for capacitor placement mount capacitors on the surface of a printed wiring board (PWB) clustered around the IC. To maximize the frequency range over which impedance is reduced, large value capacitors are placed near the power supply, mid-range value capacitors at locations between the IC and the power supply, and small value capacitors very near the IC. A large number of capacitors, interconnected in parallel, is often needed to reduce power system impedance over a wide frequency range to target levels. This distribution of capacitors is also designed to reduce response time as power moves from the power supply to the IC.
FIG. 2 is a section view of a conventional design for providing power and reducing impedance by the use of surface mount capacitors and shows the connections of Surface Mount Technology (SMT) capacitors 50 and 60 and IC device 40 to the power and ground planes in the substrate of the PWB. IC device 40 is connected to lands 41 by solder filets 44. Lands 41 are connected to plated-through hole via pads 82 and 83 of vias 90 and 100 by circuit lines 72 and 73. Via 90 is electrically connected to conductor plane 120 and via 100 is connected to conductor plane 122. Conductor planes 120 and 122 are connected one to the power or voltage side of the power supply and the other to the ground or return side of the power supply. Small value capacitors 50 and 60 are similarly electrically connected to vias and conductor planes 120 and 122 in such a way that they are electrically connected to IC device 40 in parallel.
FIG. 3 is a section view of another conventional surface mount capacitor placement design for a method of providing power and reducing impedance wherein the surface mount technology (SMT) capacitors 150 and 160 are placed on the backside (package surface opposite to that of the semiconductor) of the printed wiring board semiconductor package. The PWB semiconductor package comprises a core 170 with through hole vias 175. Build-up layers 180 are formed on each side of the core and microvias 190 connect the through hole vias 175 of the core to the surface pads 195 of the build-up layers. The power (Vcc) and ground (Vss) terminals of the semiconductor 140 are connected to the terminals of the surface mount capacitors on the back side of the PWB semiconductor package through the microvias 190 and through hole vias 175.
Similar to the surface mount capacitor placement design shown in FIG. 3, FIG. 4A depicts an Intel Pentium 4® PWB semiconductor package and shows the placement of SMT capacitors on the central area of the backside of the package. FIGS. 4A and 4B are adapted from Intel Technology Journal, Volume 9, Issue 4, 2005.
FIG. 4B shows the impedance of such an Intel Pentium 4® PWB semiconductor package. The vertical axis in FIG. 4B shows normalized magnitude of the impedance of the package and the horizontal axis shows frequency. Standard surface mount capacitors on the backside of the package (dark line in FIG. 4B) can effectively reduce impedance up to a little less than 100 megahertz (MHz). Use of low impedance array capacitors can raise this value to approximately 100 MHz due to their higher self resonant frequency. However, above 100 MHz, interconnection inductance of the capacitor circuitry begins to dominate and as can be seen from FIG. 4B, impedance rises. This interconnection inductance is due to vias extending through the thickness of the package to interconnect the capacitors to the microprocessor. Such vias are depicted by vias 175 in FIG. 3. At approximately 1 gigahertz (GHz), capacitors integrated in the semiconductor device (on-chip capacitors) reduce impedance back to lower values. Thus, the inability to effectively reduce impedance in this mid-frequency range remains a major problem to be solved.
General approaches for minimizing impedance and “noise” are known, such as that described in U.S. Pat. No. 5,161,086 to Howard et al. Howard et al. discloses a capacitive printed circuit board with one or more capacitor laminate (planar capacitor) placed within the multiple layers of the laminated printed wiring board. A large number of integrated circuits, are mounted on the board and operatively coupled with the capacitor laminate(s). The board provides capacitive function using borrowed or shared capacitance with low interconnection inductance. This approach however, does not achieve high capacitance in small PWB packages due to the low dielectric constant of the organic laminate and does not reduce impedance in the desired frequency range. Simply placing the organic capacitor laminate closer to the IC is not a satisfactory technical solution because the total available capacitance in a small PWB semiconductor package is insufficient and the capacitor laminate resonant frequency is not in the desired range.
U.S. Pat. No. 6,611,419 to Chakravorty discloses an alternate approach to embedding capacitors in order to reduce switching noise. The power supply terminals of an integrated circuit die can be coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic substrate.
U.S. Pat. App. Pub. No. 2006-0138591 to Amey et al. discloses methods for incorporating high capacitance capacitors into the core of a printing wiring board to reduce interconnection inductance and suggests that these may be placed in the build-up layers for minimized impedance. Ser. No. 11/732,174 to Borland et al. discloses a design in which capacitors are embedded in the outer layers of a printed wiring board.
Borland et al. in “Decoupling of High Performance Semiconductors Using Embedded Capacitors”, CircuiTree Live, Taiwan, October, 2006 show electrical simulation data in which an array of 200 embedded capacitors placed in the “x-y” plane of the printed wiring board within the area beneath the semiconductor (die shadow) reduced impedance to ITRS 2007 target values in the mid-frequency range between approximately 300 MHz and 1 GHz. Embedding the capacitors shifts the resonant frequencies of the capacitors to higher values as compared to surface mount capacitors due to the low inductance of the electrical interconnections of the capacitors to the semiconductor. To be effective, decoupling using embedded capacitors requires many capacitors on the layer of the printed wiring board immediately beneath the semiconductor and within the die shadow.
Generally, these previous approaches of embedding ceramic capacitors have focused on placing the capacitors on a single layer of the PWB semiconductor package as close as possible to the semiconductor. These placement approaches intend to minimize the capacitor-semiconductor electrical interconnect distance so that inductance is reduced to a minimum thereby raising resonant frequencies of the embedded capacitors as high as possible for a given size. Achieving a range of resonant frequencies is then accomplished by use of differing sized embedded capacitors.
However, reducing impedance values of semiconductor PWB packages is still needed to further semiconductor advances. Reducing the overall impedance value of a semiconductor PWB package demands the reduction of impedance at the resonant frequency of each capacitor. Since the level of impedance reduction at the capacitor resonant frequency is proportional to its capacitance, further impedance reduction requires increasing the capacitance. Assuming that the capacitance density (that is, the capacitance per unit area) of each embedded capacitor does not improve, reducing impedance means that more capacitors must be placed on one layer within the die shadow. In order to accommodate the entire range of resonant frequencies desired, the previous approaches to embedded capacitor placement would merely place more and more capacitors of differing sizes on one layer within the die shadow.
However, since the area of the PWB semiconductor package directly within the die shadow is limited, there may not be sufficient area to place enough capacitors on one layer to achieve target impedance values over the desired frequency range. What is needed is a new approach to placing capacitors within a PWB semiconductor package. This new approach would result in capacitor placement that yields sufficiently high capacitance for the likely higher impedance values of future semiconductors. This new approach would also allow the customizing (or tailoring) of the resonant frequency of the embedded capacitors to specific frequency ranges so that impedance over a targeted frequency range, such as the frequency range exhibiting the impedance peaks in FIG. 4B, namely about 100 MHz to 1 GHz, is reduced to target values.
Such an approach is not predictable by the previously discussed approaches because they do not consider, motivate or suggest a multifactor mechanism of varying the vertical placement of the embedded capacitors while positioning at least a part of the capacitor horizontally within the die shadow while simultaneously controlling the distance of the capacitor electrode terminals from the semiconductor terminals.
The methods and devices described herein provide such an unanticipated approach and solve the problem of providing a sufficient number of capacitors positioned in such a way that their resonant frequencies achieve target values, when added together reduces impedance over the desired range of frequencies of between 100 MHz and 1 to 3 GHz so that the impedance spikes shown in FIG. 4B, for example, can be eliminated.